We are a small team of expert engineers located in Austin, TX, and serving worldwide customers.

We can provide additional resources to help your project meet deadlines, or do turn-key IP development, firmware development, testbench development, complete verification, etc. testing

Why us?

At SimpleASIC, we are not confined to conventional thinking. We have a very low tolerance for complexity.  It doesn’t mean that we cannot handle complex stuff, but we handle complex stuff by breaking it down to manageable and simple components, and/or by finding better alternatives.   We approach everything as a design process with complexity as one of the key costs to optimize.  We have found that people often times introduce complexity at the benefit of other costs they can actually compromise.   For example,

• over optimize for performance.  Maybe that extra precision doesn’t actually matter much in the overall system.
• over optimize for area or speed.  Maybe you don’t need that extra speed improvement.   Maybe the area reduction doesn’t matter much at the chip level.
• reuse existing components that could have been re-designed simpler and easier.
• over optimize for plug-and-play re-usability that they don’t actually need.
• attach to design patterns or standard methodology that don’t actually fit well with their need.
• extra features they can do without.
• etc.

We stick to “clear and concise” when we write code.  Long code looks silly if you can do the same with less code, however, shorter code isn’t better unless it is also clear.   Well-commented code is better than no-commented code, but “self descriptive” code is even better than well-commented code.  Redundant code is almost always bad, but the acceptable excuse for redundant code is that “I want to make it clearer”.

We are also specialized in high-quality low-cost IP development using free open-source tools.   If you are a small company that needs something big done in a tight budget, please contact us.

Testimonials / Past Projects

• Custom digital signal processor that includes vector core and scalar core.  The C model was shared between the ISS (Instruction Set Simulator) and RTL testbench.
• SSD Controller with several cross-domain components: custom logic, PCIe standard IP, embeded CPU + firmware, host software, and external flash array.
• Mixed-signal power regulator chip that includes digital logic, analog model, CPU + firmware.

Paul led the verification of our complex mixed-signal chip and set up a new methodology to co-verify hardware and firmware.  The project would have been nowhere without his contributions.