RTL Design Tradeoffs

There are five major corners to be considered when doing an RTL design. Functionality features options precision debug features Chip area gate count storage space Speed faster clock speed less number of clock cycles Power consumption dynamic power (gate switching power) static power Simplicity development time / verification time maintainability reusability   These are called […]

Good RTL Design Starts with Good Partitioning

Few people think of RTL design as a form of object oriented programming, but inherently it is.  In testbench, you can access variables across module hierarchy but in RTL or synthesizable logic, you can’t.  So, that makes all the variables and methods inside a module local.  You have to deal with the module only through its interface […]

Floating-Point Based Testbenches

In a traditional RTL development flow, the design is pre-evaluated at the behavioral level by system simulation.  In a DSP or algorithm type of designs, the design can be evaluated with double-precision floating point math using either in C, or Matlab, or some other tools.   After performance validation, the design is then re-evaluated with finite-precision […]