These are some of the past projects we have been involved with:
- Viterbi decoder and Turbo decoder IP design for FPGA and ASIC at Hughes Network Systems.
- PCIe SSD controller hardware and firmware design at a chip startup in Austin.
- Security IP design for cable set-top box chip at Entropic Communications.
- Software Defined Radio chip design and verification at ZTE.
- Deep Belief Network algorithm (a machine learning algorithm) implementation in FPGA for a private researcher.
- LP DDR4 controller UVM-based testbench and verification at Cadence Design Systems.
- Mixed-signal power controller chip verification at Maxim Integrated.
- Vector Signal Processor design and verification at Freescale Semiconductors (now NXP Semiconductors).
- 5G New Radio baseband signal processing IP design and verification at NXP Semiconductors.
Paul is a person with multiple skill sets and a high standard of professionalism. He re-shaped our whole mixed-signal verification platform built on SystemVerilog and Verilog to make it more efficient. He hand-crafted and improved the testbench with over 200 tests, and even supported the project while he and his family were travelling to NY and overseas. He was so high efficient and dependable.
T. D., IC Design Manager at Maxim Integrated (2016)
Paul has excellent design verification and debug skills. His skills and dedication have been invaluable to
our project. Paul worked well with other team members and helped us achieve two major releases of our
IP to key customer. Despite tight schedules and many technical challenges, we were able to make the
releases on time and that would not have been possible without Paul’s outstanding contribution.
Y. P., Senior Engineering Manager at Cadence Design Systems (2017)
We were under heavy pressure to deliver a brand new IP for 5G signal processing in an extremely tight schedule. Without Paul’s contribution, this would not have been possible. He was responsible for multiple complex modules and completed them successfully and quickly. Paul is a total-package RTL designer who can understand algorithms at a higher level, write software, and also build advanced testbenches to verify his own work.
L. D., Senior Fellow at NXP Semiconductors (2019)